Junction field effect transistor level shifting circuit

ABSTRACT

A level shifting circuit can include a first driver junction field effect transistor (JFET) of a first conductivity type having a source coupled to a first supply node, a drain coupled to an output node, and a gate coupled to a first driver control node. A first driver control circuit can include a first control JFET of a second conductivity type having a source coupled to a second supply node, a gate coupled to an input node that is coupled to receive an input signal, and a first level shifting stack coupled between the source of the first control JFET and the first driver control node. The magnitude of the potential between the first supply node and the second supply node is greater than a voltage swing of the input signal.

This application claims the benefit of U.S. patent application Ser. No.11/452,442 filed on Jun. 13, 2006, which claims the benefit of U.S.Provisional Patent Application Ser. No. 60/799,787 filed on May 11,2006. The contents of both of these applications are incorporated byreference herein.

TECHNICAL FIELD

The present invention relates generally to level shifting circuits, andmore particularly to level shifting circuits that include junction fieldeffect transistors (JFETs).

BACKGROUND OF THE INVENTION

Level shifting circuits can translate an input signal that varies withinone voltage range, to an output signal that varies within another,different voltage range. Typically, level shifting circuits can beutilized to translate between logic signals operating at differentsignal voltage levels (e.g., TTL to CMOS). Level shifting circuits formetal-oxide-semiconductor (MOS) type technologies, particularly CMOStype technology are well known.

Co-pending U.S. patent application Ser. No. 11/452,442 filed on Jun. 13,2006 and U.S. Provisional Patent Application Ser. No. 60/799,787 filedon May 11, 2006, both by Ashok K. Kapoor, show examples of novelcircuits that include junction field effect transistors (JFETs) thatoperate at relatively low voltage levels (e.g., 0 to +0.5 volts). Suchcircuits can form integrated circuits that include few, or preferably noMOS type transistors. Accordingly, CMOS type level shifting circuits areof no benefit in shifting a low voltage internal signal (e.g., 0 to +0.5volts) to some higher output signal level (e.g., +1.0 volts or higher).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block schematic diagram of a level shifting circuitaccording to a first embodiment.

FIG. 2 is a block schematic diagram of an integrated circuit accordingto another embodiment.

FIG. 3 is a schematic diagram of a level shifting circuit according to athird embodiment.

FIG. 4A is a schematic diagram of a delay circuit that can be includedin the embodiment of FIG. 3. FIG. 4B is a block schematic diagram ofanother level shifting circuit according to another embodiment.

FIG. 5 is a timing diagram showing the operation of the embodiment ofFIG. 3.

FIG. 6 is a timing diagram showing the operation of the embodiment ofFIG. 3 and variations thereof, at various boosted voltage levels.

FIG. 7 is a boosted voltage generator stage according to an embodiment.

FIG. 8 is a block schematic diagram of a positive voltage generatoraccording to an embodiment.

FIG. 9 is a diagram showing the operation of the circuit of FIG. 8 andvariations thereof.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various embodiments of the present invention will now be described indetail with reference to a number of drawings. The embodiments showlevel shifting circuits and methods constructed with junction fieldeffect transistors (JFETs), for example four terminal JFETs ofcomplementary conductivity types (n-channel and p-channel types). Fourterminal JFETs can include two control terminals on different sides of achannel region.

The disclosed embodiments are in contrast to conventional level shiftingcircuits formed from complementary metal-oxide-semiconductor (CMOS) typetechnologies, constructed with MOS type transistors.

Referring now to FIG. 1, a level shifting circuit according to a firstembodiment is shown in block schematic diagram, and designated by thegeneral reference character 100. A level shifting circuit 100 canreceive an input signal INB having a first voltage swing, and generatean output signal OUTH having a second voltage swing, greater than thefirst voltage level.

In the particular example of FIG. 1, input signal INB and output signalOUTH can have an inverse relationship with one another. That is, wheninput signal INB transitions from low-to-high, output signal OUTH cantransition from high-to-low, and vice versa. In addition, in the exampleshown, input signal INB can swing between a low power supply voltageVSS, and a high power supply voltage VDDL. At the same time, outputsignal OUTH can swing between the low power supply voltage VSS and aboosted high power supply voltage VDDH that is greater than power supplyvoltage VDDL.

In the embodiment of FIG. 1, level shifting circuit 100 can include afirst control section 102, a second control section 104, a driversection 106, and a low voltage control section 108. A first controlsection 102 can control the activation of a driver control signal PUPBat a first node 114. More particularly, first control section 102 canpull first node 114 low in response to an input signal INB being low. Inthe particular example of FIG. 1, a first control section 102 caninclude a first control n-channel JFET (NJFET) N11, a first bias stackcircuit 116, and a first disable p-channel JFET (PJFET) P12. TransistorN11 can have a source connected a low power supply node 112 and a firstgate coupled to an inverting output of low voltage control circuit 108.Transistor P12 can have a source connected to boosted power supply node110, a gate connected to a disable node 118, and a drain connected to afirst driver control node 114. A bias stack circuit 116 can be connectedbetween first driver control node 114 and a drain of transistor N11.

A first bias stack circuit 116 can prevent the potential between firstdriver control node 114 and a drain of transistor N11 from falling belowa predetermined voltage. This can enable first driver control node 114to be driven at boosted voltage levels. In the particular example shown,when transistor N11 is enabled (has a low impedance), first bias stackcircuit 116 can maintain first driver control node 114 above asource-gate forward bias voltage (e.g., about 0.6 to 0.7 volts) withrespect to boosted high voltage level VDDH, that is under about 0.6volts with respect to VDDH.

A second control section 104 can control the de-activation of a drivercontrol signal PUPB at first driver control node 114. Second controlsection 104 can pull a disable node 118 low in response to an inputsignal INB being high. This, in turn, can result in transistor P11 beingturned on, and driving signal PUPB high. In the particular example ofFIG. 1, a second control section 104 can include a second control NJFETN12, a second bias stack circuit 120, and a second disable PJFET P12.Transistor N12 can have a source connected a low power supply node 112and a first gate coupled to an input node 122. Transistor P12 can have asource connected to boosted power supply node 110, a gate connected tofirst driver control node 114, and a drain connected to a disable node118. A second bias stack circuit 120 can be connected between disablenode 118 and a drain of transistor N12. A second bias stack circuit 120can operate in the same manner as first bias stack circuit 116,preventing the potential between disable node 118 and a drain oftransistor N12 from falling below a predetermined voltage.

Transistors P12 and P11 can be arranged in a cross-coupled manner, withthe gate of one being connected to the drain of the other. In thisarrangement, when a first driving signal PUPB is active (low in thisexample), transistor P12 can be turned on, pulling disable control node118 high, which turns off transistor P11, preventing current fromflowing through control section 102. Transistor P12 can be turned off,preventing current from flowing through first control section 102.Conversely, when a disable node 118 is driven low, transistor P11 can beturned on, pulling first driver control node 114 high.

In this way, control sections (102 and 104) can operate according to lowvoltage signals (IN and IN′) to drive control nodes 114 and 118 athigher boosted voltage levels. In addition, current can be conserved bypreventing current from flowing through control sections (102 and 104)regardless of output driver state (i.e., driving to a boosted high orlow).

Referring still to FIG. 1, a low voltage control section 108 can receiveinput signal INB, and in response, generate output signal IN′, which canbe the inverse of signal INB, and signal PDN, which can follow inputsignal INB. Low voltage control section 108 can operate between anon-boosted high power supply voltage VDDL and a low voltage powersupply VSS.

In this way, one driving operation (in this case a pull-down operation),can operate according to low voltage logic signals, and not includeboosted voltage signals, or circuits.

A driver section 106 can drive an output node 124 between a boosted highsupply level VDDH and a low power supply voltage VSS. In the arrangementshown, when first driving control signal PUPB is a predeterminedpotential less than a boosted high supply voltage VDDH, output node 124can be driven to a boosted high supply voltage VDDH. When first drivingcontrol signal PUPB is not a predetermined potential less than a boostedhigh supply voltage VDDH, a driver section 106 can create a highimpedance path between output node 124 and boosted high supply node 110.In this way pull-up operations to a boosted high voltage level can becontrolled.

When second driving control signal PDN is a predetermined potentialabove a low supply voltage VSS, output node 124 can be driven to a lowsupply voltage VSS. However, when second driving control signal PDN isnot a predetermined potential above low supply voltage VSS, a driversection 106 can create a high impedance between output node 124 and lowsupply node 112. In this way pull-down operations to a low voltage levelcan be controlled.

It is noted that in the example of FIG. 1, NJFETs (N11/N12) and PJFETs(P12/P11) are four terminal JFET devices, each having a front gate, backgate, source, and drain. In the example of FIG. 1, PJFET P12 has a frontgate connected to first driver control node 114, and a back gateconnected to a boosted high power supply node 110. A PJFET P22 can havea front gate connected to disable control node 118, and a back gateconnected to a boosted high power supply node 110. In addition, eachNFET and PFET can be an “enhancement” mode JFETs, as described in U.S.patent application Ser. No. 11/452,442 and U.S. Provisional PatentApplication Serial No. 60/799,787, referred to and incorporated byreference above.

In addition, low voltage control circuit 108 is preferably formed fromJFET devices, preferably, four terminal NJFET and PJFET enhancement modedevices.

Referring now to FIG. 2, one example of a semiconductor device,according to one embodiment is shown in a block diagram and designatedby the general reference character 200. A semiconductor device 200 caninclude a low voltage core section 202 and one or more level shiftingsections 204. A core section 202 can operate at a relatively lowvoltage, in this case between 0 and +0.5 volts. Preferably, a coresection 202 is formed from JFET devices, preferably complementary JFETdevices (CJFETs), even more preferably four terminal complementary JFETdevices.

A level shifting section 204 can have the general form of the circuit ofFIG. 1 or subsequently described embodiments, providing a shift involtage levels between a low voltage range of 0 to +0.5 volts, to aboosted voltage level of 0 to about +2.5 volts. However, as will bedescribed below, higher voltage levels can be accommodated.

In this way, a circuit having JFET devices operating at a power supplylevel of about +0.5 volts can generate output signals compatible withother logic types, such as complementary metal-oxide-semiconductor(CMOS) logic, as but one example. More particularly, a circuit havingJFET devices operating at about +0.5 volts and generate output signalswith swings greater than 0.5 volts.

Referring now to FIG. 3, a level shifting circuit according to anotherembodiment is shown in a schematic diagram and designated by the generalreference character 300. A level shifting circuit 300 can include someof the same general sections as FIG. 1, thus like sections are referredto by the same reference character, but with the first digit being a “3”instead of a “1”.

The example of FIG. 3 shows a level shifting circuit that can be formedfrom four terminal JFET devices of complementary conductivity type(n-channel and p-channel). Thus, within first control section 302, afirst bias stack 316′ can each include a number of NJFETs (N34 to N36)arranged in series with one another. In the particular example shown,each NJFET can have a first gate connected to its drain and a secondgate connected to its source. In such an arrangement, each such NJFETcan introduce about a 0.6 to 0.7 volt drop between a source oftransistor N21 and first driver control node 314. As a result, firstbias stack 316′ can ensure a 1.5 volt difference is maintained betweensuch nodes. Of course, FIG. 3 shows an arrangement that includes threeJFETs in a bias stack. For higher voltage levels, more JFETs could beincluded, and for lower voltage levels, fewer JFETs could be included.

Second bias stack 320′ can have the same general structure as first biasstack 316′, including NJFETs N37 to N39 arranged in series with oneanother.

In alternate embodiments, all or a portion of first and/or second biasstacks (316′ and 320′) can be replaced by diodes to introducepredetermined voltage drops through such stacks.

In this way, a level shifter can include one or more control sections(e.g., 302 and/or 304) that include stacks of JFET devices arranged inseries to ensure minimum voltage levels at control nodes (e.g., 314and/or 318). Such minimum voltage levels can enable control signals atboosted voltage levels that do not forward bias JFETs connected to theboosted voltage supply.

A low voltage control section 308′ can include logic circuits formedfrom only JFET devices, preferably only four terminal JFET devices. Forexample, a low voltage control section 308′ can include a firstinverting logic circuit 326 and a second inverting logic circuit 328arranged in series with one another. A first logic circuit 326 can havean input connected to input node 322 and an output connected a gate oftransistor N31. A second logic circuit 328 can have an input connectedto an output of first logic circuit 326, and an output that providessecond driver control signal PDN. In the very particular example shown,first and second logic sections (326 and 328) are inverters, formed withcomplementary enhancement mode JFET pairs, P33/N40 and P35/N41,respectively.

Referring still to FIG. 3, in the example shown, a driver section 306′can be formed from only JFET devices, preferably only four terminal JFETdevices. Thus, driver circuit 306′ can include a pull-up PJFET P34 and apull-down NJFET N42. Transistor P34 can have a source and back gateconnected to a boosted high power supply node 310, a front gateconnected to first driver control node 314, and a drain connected tooutput node 324. Transistor N42 can have a source and back gateconnected to a low power supply node 312, a front gate connected toreceive second driver control signal PDN, and a drain connected tooutput node 324. As understood from the above discussion, due tooperation of bias stack, a potential at the gate of transistor P34 canbe maintained at a level sufficient to prevent forward biasing of p-njunctions within transistor P34. Thus, transistor P34 can be controlledby boosted signal levels, while transistor N42 can be controlled by alow voltage signal.

It is noted that transistor P31 and P32 can be “weak” transistors ascompared to transistors within their pull-down paths (between respectivedrains and low power supply node 312). For example, a width-to-length(W/L) ratio of such transistors can be considerably smaller than NJFETsin of the pull-down path.

It is also noted that while a level shifter circuit 300 of FIG. 3preferably operates to prevent a forward biasing of p-n junctions withintransistors P31, P32 and P34, such devices can have an inherentrobustness. In the event of such a forward biasing case, such p-njunctions will clamp a potential difference to such a p-n junctionforward bias drop.

Referring still to FIG. 3, a level shifting circuit 300 can optionallyinclude a delay circuit 330 or 332. Such a delay circuit can compensatefor inherent differences in signal propagation time of the circuit inresponse to one type of transition (low-to-high) of signal INB, versusanother type of transition (high-to-low), that could otherwise result inboth driver devices P34 and N42 being turned on at the same time, andthus draw a large amounts of current. Said in another way, delaycircuits 330 or 332 can ensure driver device N42 is turned off beforetransistor P34 is turned on, or vice versa.

In the particular example of FIG. 3, it is assumed that the propagationof an input signal (INB) value signal through low voltage controlcircuit 308′ can take longer than the activation of a signal via controlsections 302 and 304. Thus, it is desirable to delay a high-to-lowtransition at first control node 314. Accordingly, a delay circuit 330can be situated between low voltage control section 208′ and a gate oftransistor N31. Delay circuit 330 can introduce more delay into ahigh-to-low transition than a low-to-high transition. This can delay theactivation of transistor P34 until after transistor N42 is fully turnedoff.

However, in the event an input signal (INB) value signal through lowvoltage control circuit 308′ takes less time than the activation of asignal via control sections 302 and 304, it would be desirable to delaya low-to-high transition in second driver control signal PDN. In such acase, a delay circuit 332 could be included between the output of lowvoltage control circuit 308′ and gate of transistor N42. Such a delaycircuit can introduce more delay into a low-to-high transition than ahigh-to-low transition.

Referring to FIG. 4A, one example of a delay circuit is shown in aschematic diagram and designated by the general reference character 400.Such a circuit can include an AND gate 402 having a delay element 404connected to one input. Such a configuration can introduce a delay intoa low-to-high transition of an input signal. Of course, FIG. 4A is butone of the many possible delay circuits than could be used to delay oneparticular type of signal transition.

Depending upon where a particular delay circuit is included within alevel shifting circuit, a different type of transition may have to bedelayed (i.e., high-to-low). In such an embodiment, a delay circuit likethat of FIG. 4B can be used. Such a delay circuit 450 can include an ORgate 452 having a delay element 454 coupled to one input. Again, FIG. 4Bis but one of the many possible delay circuits than could be used todelay one particular type of signal transition.

Referring back to FIG. 3, the particular location of a delay circuits330 or 332 are but one example of how signal delays can be introducedinto signal transitions. Other embodiments can include different circuitlocations.

Having described one particular arrangement of a level shifting circuitin FIG. 3, the operation of the circuit will now be described withreference to FIG. 5. FIG. 5 is a timing diagram showing the response ofinput signal INB, a disable node 318, a first driver control signalPUPB, signal IN′ output from low voltage control section 308′, and asecond driver control signal PDN.

Referring now to FIG. 3 in conjunction with FIG. 5, prior to time t0, aninput signal INB can be low. As a result, within first control section302, transistor N31 can be turned on, and first driver control node 314can be pulled low enough to turn on driver transistor P34 (e.g., aboutVDDH—˜0.6 volts). At the same time, within second control section 304,transistor N32 can be turned off, thus preventing a current path throughsuch a circuit. Disable transistor P32 can be turned on, pulling node318 to about VDDH. In addition, the low INB signal can be applied as alow signal PDN to a gate of driver transistor N42, turning thetransistor off. As a result, output node 324 can be at a boosted highvoltage level due to the operation of driver transistor P34, andisolated from a low supply voltage VSS by transistor N42.

At about time t0, input signal INB can transition from a low logic level(VSS) to a high logic level (VDDL). As a result, within second controlsection 304, disable node 318 can be pulled lower (e.g., about VDDH—˜0.6volts), which can turn on transistor P31. This can pull first drivercontrol node 314 high, which can turn off transistors P32 and P34,isolating output node 324 from a boosted supply voltage node 310, andpreventing current flow through second control section. In addition, byoperation of inverting logic 326 signal IN′ can go low. Within firstcontrol section 302, transistor N31 can be turned off, enablingtransistor P31 (which can be a weaker device) to pull-up first drivercontrol node 314. Still further, a signal IN′ can be inverted byinverting logic 328 to drive second driver control signal PDN high. As aresult, driver transistor N42 can be turned on, pulling output node 324down to the lower power supply level VSS.

As previously noted, in the particular example of FIG. 3 it is assumedthat signal propagation through first and second control sections (302and 304) can be faster than through low voltage control section 308′.Consequently, driver control signal PUPB can transition high at time t1,sooner than driver control signal PDN transitions high at time t2.

At about time t3, input signal INB can return to a low logic level(VSS). Within second control section 304, transistor N32 can be turnedoff. By operation of low voltage control section 308′, signal IN′ can bedriven high, and second driver control signal PDN can be driven low attime t4. However, to ensure that transistors P34 and N42 are not turnedon at the same time, delay circuit 330 can delay a low-to-hightransition in signal IN′, to ensure that transistor P34 is only turnedon at a time t5, occurring after transistor N42 is turned off.

In this way, level shifter circuit can be formed that includes only JFETdevices. More particularly, a level shifter circuit can be formed withfour terminal enhancement mode JFET devices of both n-channel andp-channel conductivities.

Referring now to FIG. 6, a timing diagram shows the operation ofvariations on a circuit like that of FIG. 3. FIG. 6 shows an inputsignal 600, such as INB of FIG. 3. Also included are various possibleoutput signals 602-0 to 602-8 corresponding to different boosted voltagelevels. Such different boost levels can be achieved by increasing thenumber of devices within bias stacks 316′ and 320′ as needed to ensure asufficiently high voltage can be maintained at nodes 314 and 318. Moreparticularly, each NJFET device within each bias stack (e.g., 316′ and320′) can provide a minimum voltage bias of about 0.6 to 0.7 volts.Thus, waveform 602-3 can correspond to circuit 300 of FIG. 3, havingthree devices within each bias stack (316′ and 320′).

In this way, increasingly higher boosted voltage levels can beaccommodated by increasing the number of devices within bias stacks.

Referring now to FIG. 7, an example of a boosted voltage generator stageaccording to an embodiment is shown in a schematic diagram anddesignated by the general reference character 700. A boosted generatorstage 700 can be used to generate a boosted voltage, like VDDH shown inthe above embodiments. The particular boosted voltage stage 700 caninclude a first stage 702, a second stage 704, and capacitors C70 andC71. First stage 702 can include an n-channel JFET N70 having asource-drain path connected between a low boost node 706 and a firstcharge node 708, and a p-channel JFET P70 having a source-drain pathconnected between first charge node 708 and a high reference node 710.Gates of JFETs P70 and N70 can be connected to second charge node 712.

A second stage 704 can include an n-channel JFET N71 having asource-drain path connected between low boost node 706 and a secondcharge node 712, and a p-channel JFET P71 having a source-drain pathconnected between second charge node 712 and a high reference node 710.Gates of JFETs P71 and N71 can be connected to first charge node 708.Capacitor C70 can have one terminal connected to first charge node 708and another terminal that receives a periodic clock signal CLK1.Capacitor C71 can have one terminal connected to second charge node 712and another terminal that receives a periodic clock signal CLK2, whichcan be essentially the inverse of clock signal CLK1.

In operation, when signal CLK1 is low and signal CLK2 is high,previously charged capacitor C71 can drive second charge node 712 abovethe potential at low reference node 706. JFET P71 can be turned on andJFET N71 can be turned off, thus driving high boost node 710 to apotential higher than high reference node 710. At the same time, JFETN70 can be turned on and JFET P70 can be turned off, connecting firstcharge node 708 to low reference node 706. Signal CLK1 can chargecapacitor C70 to a potential lower than low reference node 706.

When signal CLK1 is high and signal CLK2 is low, previously chargedcapacitor C70 can drive first charge node 708 above the potential athigh reference node 710. JFET P70 can be turned on, and JFET N70 can beturned off, thus driving high boost node 710 to a higher potential thanhigh reference node 710. At the same time, JFET P71 can be turned offand JFET N71 can be turned on, connecting second charge node 712 to lowreference node 706. Signal CLK2 can charge capacitor C71 to a potentiallower than low reference node 706.

In the example of FIG. 7, all JFETs can be four terminal JFETs, having afirst control gate and second control gate separated from one another bya channel region. First gate connections for such transistors have beendescribed above. In addition, second gates of JFETs N70 and N71 can becommonly connected to low boost node 706, while second gates of JFETsP70 and P71 can be commonly connected to a high reference node 710.

In this way, a boosted voltage generator stage can generate a boostvoltage utilizing JFETs, preferably complementary four terminal JFETs.

While a single boosted voltage generator stage, like that of FIG. 7, canprovide a given boosted voltage. It may be desirable to provide boostedvoltages of even greater magnitude. In such a case, several generatorstages like that of FIG. 7 can be connected in series to form a voltagegenerator circuit. One example of such an arrangement is shown in FIG.8.

FIG. 8 shows a voltage generator 800 that can include a number ofgenerator stages 802-1 to 802-N, each of which can take the form ofgenerator stage 700 shown in FIG. 7. A last generator stage 802-N canhave a low boost node connected to a boosted supply node 806. Acapacitor C80 can be connected between boosted supply node 806 and areference supply node 804. A next to last generator stage 802-N-1 canhave a high boost node (VHI) connected to a low reference node (VLO) ofnext stage (i.e., 802-N). Each generator stage can be connected to thenext stage in this fashion, ending with a first generator stage 802-1,which can have a low reference node VLO connected to a high supply node808. Clock signals CLK1 and CLK2 can be connected to generator stages(802-1 to 802-N) in an alternating fashion with respect to a first clockinputs CLKI1 and a second clock inputs CLKI2.

In this way, a series of generator stages can be connected together togenerate boosted voltage levels of greater magnitude.

Referring now to FIG. 9, a timing diagram shows the response of avoltage generator, like that shown in FIG. 8, having six stages (e.g.,N=6). FIG. 9 includes six waveforms, each of which shows a potential ata high boost node (VHI) of each stage over time. Waveforms 900, 902,904, 906, 908 and 910 show the responses of generator stages 802-N to802-1, respectively.

It is understood that reference in the description to “one embodiment”or “an embodiment” means that a particular feature, structure, orcharacteristic described in connection with the embodiment is includedin at least one embodiment of the invention. The appearance of thephrase “in one embodiment” in various places in the specification do notnecessarily all refer to the same embodiment. The term “to couple” or“electrically connect” as used herein may include both to directly andto indirectly connect through one or more intervening components.

Further it is understood that the embodiments of the invention may bepracticed in the absence of an element or step not specificallydisclosed. That is an inventive feature of the invention may include anelimination of an element.

While various particular embodiments set forth herein have beendescribed in detail, the present invention could be subject to variouschanges, substitutions, and alterations without departing from thespirit and scope of the invention. Accordingly, the present invention isintended to be limited only as defined by the appended claims.

1. A level shifting circuit, comprising: a first driver junction fieldeffect transistor (JFET) of a first conductivity type having a sourcecoupled to a first supply node, a drain coupled to an output node, and agate coupled to a first driver control node; a first driver controlcircuit comprising, a first control JFET of a second conductivity typehaving a source coupled to a second supply node, a gate coupled to aninput node that is coupled to receive an input signal, and a first levelshifting stack that prevents a potential between the drain of the firstcontrol JFET and the first driver control node from falling below apredetermined limit; wherein the magnitude of the potential between thefirst supply node and the second supply node is greater than a voltageswing of the input signal.
 2. The level shifting circuit of claim 1,wherein the first driver JFET comprises a p-channel JFET and the firstsupply node is a first high supply voltage node; the first control JFETcomprises an n-channel JFET and the second supply node is a low supplyvoltage node.
 3. The level shifting circuit of claim 2, wherein: thefirst driver JFET and first control JFET comprise four terminal JFETs,each having a first control gate separated from a second control gate bya channel region.
 4. The level shifting circuit of claim 1, wherein: thefirst level shifting stack comprises a plurality of stack JFETs of thesecond conductivity type having source-drain paths coupled in series, atleast a first gate of each stack JFET being coupled to its source. 5.The level shifting circuit of claim 1, further including: the firstdriver control circuit further includes a disable JFET of the firstconductivity type having a source coupled to the first supply node, adrain coupled to the first driver control node, and a gate coupled to adisable node; a disable control circuit comprising, a second controlJFET of the second conductivity type having a source coupled to thesecond supply node, a gate coupled to the input node, and a second levelshifting stack that prevents a potential between the drain of the secondcontrol JFET and the disable node from falling below the predeterminedlimit.
 6. The level shifting circuit of claim 1, wherein: a seconddriver JFET of the second conductivity type having a source coupled tothe second supply node, a drain coupled to the output node, and a gatecoupled to a second driver control node; and a low voltage controlcircuit that operates between voltage swing levels of the input signal,the low voltage control circuit being coupled between the input node andthe second driver control node.
 7. The level shifting circuit of claim6, wherein: the second driver control circuit couples the input node tothe gate of the first control JFET.
 8. A level shifting circuit,comprising: a driver section that includes a first driver junction fieldeffect transistor (JFET) of a first conductivity type having asource-drain path coupled between a first supply node and an outputnode, and a gate coupled to a first driver control node, and a seconddriver JFET of a second conductivity type having a source-drain pathcoupled between a second supply node and the output node, and a gatecoupled to a second driver control node; and a low voltage controlcircuit comprising a plurality of JFETs that couples an input node tothe second driver control node, the low voltage control circuit beingcoupled between the second supply node and a third supply node; whereinthe magnitude of the potential between the first supply node and thesecond supply node is greater than the magnitude of the potentialbetween the third supply node and the second supply node.
 9. The levelshifting circuit of claim 8, wherein: the low voltage control circuitcomprises at least one control JFET of the first conductivity typehaving a source coupled to the third supply node, and at least onecontrol JFET of the second conductivity type having a source coupled tothe second supply node.
 10. The level shifting circuit of claim 8,further including: the input node is coupled to receive an input signal;and a driver enable circuit that includes an enable control devicecoupled in series with an enable bias stack between the first drivercontrol node and the second supply node, the enable control deviceproviding a low impedance path in response to the input signal having afirst logic level, the enable bias stack preventing a voltage across theenable bias stack from falling below a predetermined limit.
 11. Thelevel shifting circuit of claim 10, further including: a driver disablecircuit that includes a disable control device in series with a disablebias stack coupled in series between a disable node and the secondsupply node, the disable control device providing a low impedance pathin response to an input signal having a second logic level, the disablebias stack preventing a voltage across the disable bias stack fromfalling below the predetermined limit; and a disable device thatprovides a low impedance path between the first driver control node andthe first supply in response to the potential at the disable node. 12.The level shifting circuit of claim 11, wherein: the enable stack anddisable stack each comprise a same number of JFETs coupled to oneanother in series.
 13. The level shifting circuit of claim 10, wherein:the low voltage control circuit includes a first inverting section thatinverts the input signal to generate an inverse signal at a firstsection output, the first section output being coupled to the enablecontrol device, and a second inverting section that inverts the inversesignal to generate a control signal at a second section output, thesecond section output being coupled to the second driver control node.14. The level shifting circuit of claim 10, further including: an edgedelay circuit coupled between the input node and the driver enablecircuit, the edge delay circuit introducing a greater delay intotransitions from a first signal level to a second signal level, thantransitions from the second signal level to the first signal level. 15.A level shifting circuit, comprising: a first control section coupledbetween a boosted power supply node and a first power supply node thatincludes a first disable junction field effect transistor (JFET) of afirst conductivity type having a source-drain path coupled between theboosted power supply node and a first driver control node, a firstcontrol JFET of a second conductivity type having a source-drain pathcoupled to the first power supply node, and a gate coupled to receive aninput signal having a voltage swing less than a difference in potentialbetween the boosted power supply node and the first power supply node,and a first bias circuit having first and second terminals coupledbetween the first driver control node and the first control JFET,respectively that ensures a minimum voltage is maintained between thefirst and second terminals.
 16. The level shifting circuit of claim 15,wherein: the first bias circuit comprises a plurality of JFETs coupledin series with one another.
 17. The level shifting circuit of claim 15,further including: the first disable JFET having a gate coupled to adisable node; a second control section coupled between the boosted powersupply node and the first power supply node that includes a seconddisable JFET of the first conductivity type having a source-drain pathcoupled between the boosted power supply node and the disable node, asecond control JFET of the second conductivity type having asource-drain path coupled to the first power supply node, and a secondbias circuit having third and fourth terminals coupled between the firstdriver control node and the first control JFET, respectively, that thatensures a minimum voltage is maintained between the third and fourthterminals.
 18. The level shifting circuit of claim 15, furtherincluding: a driver section that includes a first driver JFET of thefirst conductivity type having a source drain path coupled between theboost supply node and an output node, and a gate coupled to the firstdriver control node.
 19. The level shifting circuit of claim 18, furtherincluding: a low voltage control section coupled between an input nodeand a second driver control node that outputs a low voltage controlsignal having the same voltage swing as the input signal; and the driversection further includes a second driver JFET of the second conductivitytype having a source-drain path coupled between the output node and thefirst power supply node, and a gate coupled to the second driver controlnode.
 20. The level shifting circuit of claim 15, wherein: the firstdisable JFET and a first control JFET comprise four terminal JFETs, eachhaving a source terminal, drain terminal, first gate terminal and secondgate terminal separated from the first gate terminal by a channelregion.